The present invention relates to a circuit design support apparatus and a method to partially convert a description of a circuit model to quickly simulate the circuit model in a CAD system.
Recently, in proportion to the scale of design object hardware such as LSI, CAD systems have been developed to support a high level design such as functional design for the purpose of improving design efficiency. In this case, as input data to a simulator (except for the drawing input), a hardware description language (HDL) for hardware design, which is similar to software programming language, is used. A designer inputs the drawing or HDL to the simulator and verifies the design by simulation. HDL, such as VHDL and Verilog HDL supports mixed-level simulation. In short, single HDL supports a plurality of description levels (method) as a model description. The plurality of description levels is combined and verified. Therefore, this method is used by many designers.
A unit described in simulation model to activate in parallel is called xe2x80x9cprocessxe2x80x9d. FIG. 1 shows one example of a process described by VHDL. FIG. 2 shows one example of a process by Verilog HDL. In FIG. 1, the process of VHDL executes when signals xe2x80x9cin 1xe2x80x9d xe2x80x9cin 2xe2x80x9d located next to a reserved word xe2x80x9cprocessxe2x80x9d change. In FIG. 2, the process of Verilog HDL executes when signals xe2x80x9cin 1xe2x80x9d xe2x80x9cin 2xe2x80x9d located next to a reserved word xe2x80x9calways xc3xa2xe2x80x9d change. A list of signals xe2x80x9cin 1xe2x80x9d xe2x80x9cin 2xe2x80x9d is called a sensitivity list of process, and the signal is called a sensitivity signal (driving signal).
In order to support the high level design, the simulator must be able to quickly simulate a large scale circuit. Therefore, the large scale circuit is not simulated by a simulator of an event-driven method as the prior art but rather is simulated by a simulator of a cycle-base method as a high speed method. In the event-driven method, if an input to an element changes at an interval, an output from the element is logically calculated at the next interval. Otherwise, the output is not calculated. For example, as shown in FIG. 3, if signal B is input to an AND circuit {circle around (1)}, an output signal E from the AND circuit {circle around (1)} is calculated and an output signal G from an AND circuit {circle around (3)} is calculated. In this way, by detecting a change of the signal value (event), the signal value is transmitted in order. When all signals do not change, the timing is updated. In the cycle-base method, a dependence relation of the processing of the simulation model is previously analyzed. The execution order of the process is determined so that its pulse coincides with a simulation result of the event-driven method by one clock pulse. The circuit is basically evaluated at one time by one clock pulse. The cycle-base simulation is used not for verification of timing, but for fast verification of function. Therefore, the delay described in the assignment of signals, except for the clock signal, is ignored. In case of event-driven simulation, the signal value changes many times in one clock pulse. However, in case of cycle-base simulation, the signal value changes once every clock pulse and the simulation is quickly executed. For example, as shown in FIG. 4, a signal is inputted to two registers by a first clock, and the signal is then respectively-outputted from the two registers to the AND circuit {circle around (1)} and OR circuit {circle around (2)} by a second clock. Next the signal is respectively outputted from the AND circuit {circle around (1)} and the OR circuit {circle around (2)} to AND circuit {circle around (3)} by a third clock, and the signal is outputted from the AND circuit {circle around (3)} by a fourth clock. In this way, in the cycle base method, the signal value is transmitted in one clock pulse. Therefore, management processing of clock timing requires a large load. In addition to this, signals in the register includes various kinds of information (previous signal value, input time and so on) and the signals with the various kinds of information are transmitted in the circuit. Therefore, the register processing for signal transmission requires a large time cost.
As another fast simulation method, a plurality of modules in the large scale circuit consists of a combined register transfer level model and a behavior level model. In general, all modules in the circuit are described by the register transfer level based on the construction of hardware. In this method, as for a debugged module in a large scale circuit, the designer creates a new behavior level model based on activation of a hardware model, or buys a model on the market. The behavior level model is combined with the register transfer level model in the large scale circuit to increase the simulation speed. However, it costs a great deal to create a different level model or to buy the model on the market, and verification for each model is necessary. Therefore, the design period is not effectively reduced. Furthermore, these models are independently created and inconsistent with each other in the circuit. Therefore, inconvenience occurs in management of these models as a circuit design. Furthermore, a test vector must be respectively prepared for each of these models. In short, use of the plurality of models is not adequate as a fast simulation means.
It is an object of the present invention to provide a circuit design support apparatus and a method to partially convert a simulation model to greatly reduce the simulation time.
According to the present invention, there is provided a circuit design support apparatus to partially convert a description of a circuit model to quickly simulate, comprising: a register signal replacement means for replacing a register signal as a variable in a process related to the register signal of the description, and inserting a declaration of the variable in the process instead of a declaration of the register signal in the description.
Further in accordance with the present invention, there is also provided a circuit design support apparatus to partially convert a description of a circuit model to quickly simulate, comprising: a clock signal simplification means for replacing a clock signal as a variable in a clock signal reference process of the description, and for unifying a clock signal update process to the clock signal reference process in the description.
Further in accordance with the present invention, there is also provided a circuit design support apparatus to partially convert a description of a circuit model to quickly simulate, comprising: a clock signal simplification means for deleting a declaration of a clock signal and a clock signal update process in the description, and for creating a plurality of clock signal reference processes in order by unit of value of the clock signal in the description.
Further in accordance with the present invention, there is also provided a circuit design support method for partially converting a description of circuit model to quickly simulate, comprising the steps of: replacing a register signal as a variable in a process related with the register signal of the description; and inserting a declaration of the variable in the process instead of a declaration of the register signal in the description.
Further in accordance with the present invention, there is also provided a circuit design support method for partially converting a description of circuit model to quickly simulate, comprising the steps of: replacing a clock signal as a variable in a clock signal reference process of the description; and unifying a clock signal update process to the clock signal reference process in the description.
Further in accordance with the present invention, there is also provided a circuit design support method for partially converting a description of circuit model to quickly simulate, comprising the steps of: deleting a declaration of a clock signal and a clock signal update process in the description; and creating a plurality of clock signal reference processes in order by unit of value of the clock signal in the description.
Further in accordance with the present invention, there is also provided a computer readable memory containing computer readable instructions to partially convert a description of circuit model to quickly simulate, comprising: an instruction means for causing a computer to replace a register signal as a variable in a process related to the register signal of the description; and an instruction means for causing a computer to insert a declaration of the variable in the process instead of a declaration of the register signal in the description.
Further in accordance with the present invention, there is also provided a computer readable memory containing computer readable instructions to partially convert a description of circuit model to quickly simulate, comprising: an instruction means for causing a computer to replace a clock signal as a variable in a clock signal reference process of the description; and an instruction means for causing a computer to unify a clock signal update process to the clock signal reference process in the description.
Further in accordance with the present invention, there is also provided a computer readable memory containing computer readable instructions to partially convert a description of circuit model in order to quickly perform a simulation, comprising; an instruction means for causing a computer to delete a declaration of a clock signal and a clock signal update process in the description; and an instruction means for causing a computer to create a plurality of clock signal reference processes in order by unit of value of the clock signal in the description.